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Scheduling periodic real-time tasks on multiple periodic resources is an emerging research issue in the real-time scheduling community and has drawn increased attention over the last few years. This paper studies a sub-category of the scheduling problem which focuses on scheduling a periodic task on multiple periodic resources where none of these resources have sufficient capacity to support the task. Instead of splitting the task into sub-tasks, which is not always practical in real systems, we integrate resources together to jointly support the task. First, we develop a method to integrate two fixed but arbitrary pattern periodic resources into an equivalent periodic resource. Second, for two periodic resources with unknown but fixed resource occurrence patterns, we give the lower and upper bounds of the available time provided by an integrated periodic resource within a period. Third, we present theoretical and empirical analysis on the schedulability of a non-splittable periodic task on two periodic resources and their integrated periodic resource.

This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. © Springer International Publishing Switzerland 2015.

Search task difficulty has been attracting much research attention in recent years, mostly regarding its relationship with searchers' behaviors and the prediction of task difficulty from search behaviors. However, it remains unknown what makes searchers feel the difficulty. A study consisting of 48 undergraduate students was conducted to explore this question. Each participant was given 4 search tasks that were carefully designed following a task classification scheme. Questionnaires were used to elicit participants' ratings on task difficulty and why they gave those ratings. Based on the collected difficulty reasons, a coding scheme was developed, which covered various aspects of task, user, and user-task interaction. Difficulty reasons were then categorized following this scheme. Results showed that searchers reported some common reasons leading to task difficulty in different tasks, but most of the difficulty reasons varied across tasks. In addition, task difficulty had some common reasons between searchers with low and high levels of topic knowledge, although there were also differences in top task difficulty reasons between high and low knowledge users. These findings further our understanding of search task difficulty, the relationship between task difficulty and task type, and that between task difficulty and knowledge level. The findings can also be helpful with designing tasks for information search experiments, and have implications on search system design both in general and for personalization based on task type and searchers' knowledge. (C) 2014 Elsevier Ltd. All rights reserved.

Data dissemination protocols govern interaction and exchange of data among nodes in a distributed system. An understanding of data transfer protocols provides insight into efficient middleware management. Due to their simplicity, scalability and fault-tolerance, gossip-based protocols are researched widely as an effective communication strategy. The Shuffle protocol presented in [1], is an example of a decentralized, gossip-based data transfer protocol used to spread information in a wireless network via probabilistic exchange of data. This paper presents, an asynchronous variant of the Shuffle protocol and a system model that captures variability in data transmission times. This transmission time variability is inherent in dynamic networks, where such algorithms are typically deployed. A simulation-based analysis of the protocol's performance behavior is presented. Results show the effects of transmission variability, on data replication and its coverage. Also examined is the relationship between available storage and the performance of the protocol, expressed using measures such as propagation time and work. © 2015 IEEE.

Manufacturers of CPUs publish a document that contains information about the processor that includes: list of registers, function of each register, size of data bus, size of address bus and list of instructions that can be executed by the CPU. Each CPU has a known instruction set that a programmer can use to write assembly language programs. Instruction sets are specific to each type of processor. That being said, Pentium processors use a different instruction set than ARM processors. Using the Instructions a of processor to write a program is called assembly language and function of an assembler is to convert assembly language to machine code (binary) that the CPU can understand.

ARM offers variety of the core processor base on their applications and they are: Cortex A series: Cortex A series is a High performance processor for open operating system, the Cortex-A50 is a 64 bit process, application of Cortex-A series are Smart phones, Netbook, Digital TV, and eBook readers

The data transfer instructions are used to transfer data from memory to registers and from registers to memory and they are Load (LDR) and Store (STR) instructions.

Advanced RISC Machine (ARM) was developed by the Acorn Company. ARM is a leader supplier of microprocessors in the world, ARM develop the core CPU and thousand of suppliers add more functional units to the core. ARM uses two types instruction called Thumb and Thumb-2. Thumb instructions are 16 bits and thumb-2 instructions are 32 bits, currently most ARM processors uses 32 bit instructions.

The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are three basic logic operations and they are called AND, OR and NOT.

In order to understand network technology it is important to know how information is represented for transmission from one computer to another. Information can be transferred between computers in one of two ways: an analog signal or a digital signal.

Dynamic voltage and frequency scaling (DVFS) is a well-known technique to optimize the power dissipation of electronic systems without significantly compromising overall system performance. DVFS exploits the periods of inter-core data exchange (memory-bound operations) to reduce the voltage and frequency (V/F) of the cores in order to reduce the power dissipation during the execution flow of an application running on the CMP. As the lengths of the idle and busy periods of the cores vary depending on the benchmarks, it is crucial for any DVFS technique to maximize the power saving without losing a significant performance. In this work we present two power optimization methodologies that are integrated into a full-system simulator to make online predictions about the voltage and frequency of the cores during the execution time of the benchmarks. We evaluate these methodologies in terms of the V/F predictions vs. the actual utilization of each core periodically. We also compare the overall execution time, energy dissipation, and energy-delay product (EDP) of the power optimization methodologies for various benchmarks. © 2015 IEEE.

We find that the relative preference of hedonic products is disproportionately enhanced when they are offered at a free price. This “free price bounce” is more subdued for utilitarian products. This is surprising because rational choice theory posits that relative preference amidst two options - say a hedonic and a utilitarian product - remains intact as long as the price difference between them is constant. We propose and demonstrate that this axiom is violated when a hedonic product is offered for free. (C) 2015 Elsevier B.V. All rights reserved.