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Dynamic voltage and frequency scaling (DVFS) is a well-known technique to optimize the power dissipation of electronic systems without significantly compromising overall system performance. DVFS exploits the periods of inter-core data exchange (memory-bound operations) to reduce the voltage and frequency (V/F) of the cores in order to reduce the power dissipation during the execution flow of an application running on the CMP. As the lengths of the idle and busy periods of the cores vary depending on the benchmarks, it is crucial for any DVFS technique to maximize the power saving without losing a significant performance. In this work we present two power optimization methodologies that are integrated into a full-system simulator to make online predictions about the voltage and frequency of the cores during the execution time of the benchmarks. We evaluate these methodologies in terms of the V/F predictions vs. the actual utilization of each core periodically. We also compare the overall execution time, energy dissipation, and energy-delay product (EDP) of the power optimization methodologies for various benchmarks. © 2015 IEEE.

1 citations (Crossref) [2023-10-31] tex.type: Proceedings paper