Systolic architectures for parallel Fourier transform
Resource type
Authors/contributors
- Baradaran-Seyed, T. (Author)
- Johnson, L.G. (Author)
- Karimi, B. (Author)
Title
Systolic architectures for parallel Fourier transform
Abstract
New systolic architectures are proposed for the computation of the Fourier transform based on the generation of the coefficients of the transform during the computation. These architectures require less input/output pins on the chip. The new architectures are also extremely modular and cascadeable, thus, amenable for efficient VLSI implementation. VLSI complexity of the architectures are compared with the existing parallel architectures. © 1992 IEEE.
Proceedings Title
Midwest Symposium on Circuits and Systems
Publisher
Institute of Electrical and Electronics Engineers Inc.
Date
1991
Pages
283-286
ISBN
15483746 (ISSN); 0780306201 (ISBN)
Citation Key
baradaran-seyedSystolicArchitecturesParallel1991
Archive
Scopus
Language
English
Extra
0 citations (Crossref) [2023-10-31]
Journal Abbreviation: Midwest Symp Circuits Syst
Citation
Baradaran-Seyed, T., Johnson, L. G., & Karimi, B. (1991). Systolic architectures for parallel Fourier transform. Midwest Symposium on Circuits and Systems, 283–286. Scopus. https://doi.org/10.1109/MWSCAS.1991.252044
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